32 Fiber Photonic Plug
A fiber connector product for assembly of optical fibers with silicon photonics chip.
The product is optimized for co-packaged optics stacks with high compatibility to flip-chip and reflow packaging processes.
Key Features
High assembly tolerance of >+/-20um/1dB for assembling single-mode fiber ribbon to a silicon photonics chip.
Supports multi-fiber, up to 12, silicon photonics packaging for transceiver and co-packaged optics products.
Uses passive assembly protocols and supports high volume packaging using standard semiconductors manufacturing and packaging flows.
Supports wavelength division multiplexing (WDM) die stacking with surface-coupling geometries
Incorporates wafer level optical elements for seamless integration of optical and electrical bumps.
Specifications
| Parameter | Property | |
| Fiber arrangement | Fiber type | Single-mode |
| Fiber array | 32 | |
| Pitch | Typical: 250μm (Optional 127μm pitch) |
|
| Fiber array length | Typical 5-100cm Flexibility for other lengths |
|
| Connector | Typical: MPO Optional: FC/APC, LC/FC ferrule and various termination methods |
|
| Material | PP stack | PP Si die, Glass spacer, Single Mode fiber array |
| Die substrate | Silicon | |
| Coating | Au | |
| Glass attach to PP die | PP Si die, Glass spacer, Single Mode fiber array | |
| Insertion loss | PP loss | <1/dB |
| Spectral | Bandwidth | O and C bands |
| Back reflection | <45dB | |
| Footprint | Dimensions PP 12Fibers | 5.0mmx3.9mmX1.0mm |
| PP assembly on PIC | Assembly method | Passive assembly via machine vision |
| Attach to PIC | Adhesive | |
| PP assembly tolerances | XYZ | ±20µm / 1dB loss |
| Rotation | ±1 deg / 0.5dB loss | |
| Tilt | ±2mRad / 0.3dB loss |
Applications
Transceivers
Scalable fiber assembly for silicon photonics 400G, 800G, 1.6T, 3.2T transceivers
Requirements
Requirements
PhotonicPlug connectivity requires an add-on element, called PhotonicBump, implemented on silicon photonics wafer through wafer level process
PhotonicBump is part of the “self-aligning optics” scheme which enables large assembly tolerance when integrated with PhotonicPlug connector device.
PhotonicBump for WDM silicon photonic chip:
- Optical elements on silicon photonics wafer for replacing side-coupling by wide-band surface coupling
- Provides mode conversion to match single-mode beam diameter
- Requires a cavity etch through CMOS foundry process and post process of wafer level optics
PhotonicBump for grating coupler based silicon photonic chip:
- Optical elements on silicon photonics wafer for enabling PhotonicPlug “self-aligning optics” scheme
- Requires a CMOS wafer level process on silicon photonics’ top passivation layer (at Foundry or OSAT)
PhotonicBump for WDM chip specifications
| Parameter | Property |
| Wide-band Photonic-Bump | Cavity via CMOS process at SiP foundry and post process optics implementing (at Foundry or OSAT) |
| Wide Band beam deflection angle | 10o (other customized angles are available ) |
| Mode conversion | ~4µm to 9µm |
| Cavity dimensions | Width: 200µ width, Depth: down to 15µm |
| Coating | Al / Au |
| Footprint required on silicon photonics for PP placement | W=2.0mm, H=1.0mm, L=up to # of channels and pitch |
PhotonicBump for grating coupler specifications
| Parameter | Property |
| GC Photonic-Bump | CMOS process at silicon photonics foundry implemented on top passivation layer |
| Surface coupling | 10o (other customized angles are available ) |
| Bump Dimensions | 120×120µm |
| Footprint required on silicon photonics for PP placement | W=2.0mm, H=1.0mm, L=up to # of channels and pitch |