Our Technology

Seamlessly connect optics to silicon

The Universal Photonic Coupler uses multiple proprietary breakthrough technologies for scalable photonic packaging

Self-aligning optics

Patented 3D optical design for unprecedented fiber-chip assembly tolerances


Versatile design supporting various customer use-cases, optical arrangements and fiber characteristics


Wafer-level optical elements for significantly increased reliability and high yield silicon photonics manufacturing, testing and packaging

Wideband surface coupling

Wideband surface coupling that avoids complicated side-coupling geometries

Detachable fiber connectivity

Detachable fiber connectivity optimized for co-packaged optics, high fiber count and post reflow assembly

Self-aligning optics for large assembly tolerances

Teramount’s patented self-aligning optics technology, realized within the Photonic-Plug and Photonic-Bump components, offers better than ±30µm / 0.5dB of assembly tolerances when aligning single-mode (SM) or polarization-maintaining (PM) fibers to a silicon photonics chip.

Large assembly tolerances are a key issue for the enablement of large number of fibers passive assembly protocols. In addition, it is crucial for enhancing system thermal management.

Wafer-level manufacturing of optical elements in Teramount’s Photonic-Plug.
Measured XY fiber assembly tolerances of Teramount’s Universal Photonic Coupler (Right) compared with the tight tolerances of direct fiber side-coupling (left).
Measured tolerances cross-section better than ±30µm / 0.5dB with Teramount’s Universal Photonic Coupler.

The Photonic-Plug

Incorporating wafer-level optical elements for enabling
Teramount’s patented “self-aligning optics” technology.

The Photonic-Plug makes use of wafer-level processes for
accurate placement of optical elements, thus shifting
accuracy requirements from assembly to wafer
manufacturing domain.

Unparalleled scalability with 127µm fiber pitch and 32+ SM/PM fibers
in a single-row configuration, or 64µm effective fiber pitch and 64+ SM/PM
fibers in a Double-decker configuration, thanks to the planar separation design,
which moves fibers from the PIC/Waveguide plane to the Photonic Plug.

Versatile design easily adapts to customer’s use-case and
PIC characteristics (Detachable vs. Bonded, Waveguide vs.
Grating Coupling, Fiber pitch & count, Expanded Beam, etc…).

Unparalleled bandwidth density in Photonic-Plug
with 32+ SM/PM fibers @ 127µm fiber pitch
Industry-leading shoreline density with Photonic-Plug Double-decker configuration, supporting 64+ SM/PM fiber @ 64µm fiber pitch

The Photonic-Bump

Teramount’s Photonic-Bump aligns photonics with standard semiconductor manufacturing, packaging, and testing flows. The Photonic-Bump is a wafer-level optical element attached on the customer’s silicon photonics PIC wafer and accurately placed relative to a tapered waveguide using wafer-level processes.
The Photonic-Bump enables the following key features:

  • Beam deflection from a horizontal waveguide’s taper to a vertical axis for surface coupling. A deflector mirror is used to obtain wideband surface coupling and replace typical side-coupling.
  • Mode-matching and spot-size conversion for matching waveguide and single-mode fiber spot sizes.
  • Beam expansion for large assembly tolerances via “Self-aligning Optics” technology, when combined with Teramount’s Photonic-Plug.
  • Wafer-level testing, allowing surface probing of silicon photonics wafers before dicing.
  • Planar separation between fibers and silicon photonics chip for efficient optical and electrical packaging.

Teramount offers Photonic-Bump variants for both tapered waveguides and grating couplers, enabling unprecedented tolerances, passive assembly, and efficient wafer-level testing.

Photonic-Bump for WDM chips: Wafer-level optics for Beam-deflection, Spot-size conversion and “Self-aligning Optics”.
Photonic-Bump for grating coupling-based chips: Providing Beam-expansion and "Self-aligning Optics”.
PIC wafer with Photonic-Bumps attached to PICs.

Wideband surface coupling

Teramount’s Universal Photonic Coupler incorporates beam-deflection optics optimized for WDM silicon photonics chips. It enables wideband surface-coupling, with the following key features:

  • 32+ SM/PM fibers with 127µm pitch, connected to a customer’s PIC, for excellent scalability.
  • Excellent Insertion Loss Performance per channel, under 1.5dB from facet to waveguide.
  • Polarization Agnostic.
  • Passive alignment, for a much higher assembly and testing throughput.
  • Wafer-level Testing support, significantly increasing production yield
  • 2.5/3D Packaging compliant, with full support for thinned PICs and Through-Silicon Vias

With Teramount’s wideband surface coupling, PIC designers finally have the ultimate fiber coupling solution suitable for high-volume manufacturing and can avoid the many limitations of legacy side coupling and narrowband surface coupling.

The Photonic-Bump’s wafer-level optics enabling wideband surface-coupling and wafer-level inspection.

Detachable fiber connectivity:
Game changer for co-packaged optics

  • Detachable Universal Photonic Coupler ushers in a new era of detachable and serviceable fiber connectivity for co-packaged optics.
  • Post reflow assembly, improving packaging yield.
  • Effective PIC testing pre- and post-fiber assembly through Teramount’s Photonic-Bump and planar coupling geometry.
  • Large number of fibers for co-packaged optics and high bandwidth applications.
  • No mid-board connector: One fiber ribbon from PIC to faceplate for higher optical throughput and improved insertion loss.
Detachable fiber connectivity: a game changer for co-package optics in networking and advanced computing applications.
Detachable Photonic-Plug: Unprecedented assembly tolerances for serviceable and detachable fiber assembly.
High yield packaging: Post-reflow assembly, pre- and post-fiber assembly testing, supporting high fiber count.
“With Teramount’s solution, photonics can now be seamlessly integrated with electronics,
providing our customers with unparalleled high bandwidth and low power consumption”