Our Technology

Seamlessly connects optics to silicon

Teramount PhotonicPlug uses multiple proprietary breakthrough technologies for scalable photonic packaging

Self-aligning optics

Patented wafer level optics for unprecedented fiber-chip assembly


Wafer level optical elements for reliable and high yield silicon photonics manufacturing, testing and packaging

Wide-band surface coupling

Wide-band surface coupling that avoids complicated side-coupling geometries

Detachable fiber connectivity

Detachable fiber connectivity optimized for co-packaged optics, fiber high count and post reflow assembly

Self-aligning optics for large assembly tolerances

PhotonicPlug incorporates a wafer level optical elements for enabling Teramount patented “self-aligning optics” scheme. Such optical arrangement offers >±20um/1dB of assembly tolerances when aligning single-mode fiber to a silicon photonic chip.

PhotonicPlug takes advantage from wafer level processes for accurate placement of optical elements thus shifts accuracy requirements from assembly to wafer manufacturing domain

Large assembly tolerance is a key issue for enablement of large number of fibers passive assembly protocols. In addition, it is crucial for enhancing system thermal management.

PhotonicPlug wafer level manufacturing of optical elements
PhotonicPlug measured XY fiber assembly tolerances (Right) compared with a tight tolerance of direct fiber coupling (left)
Measured tolerance cross section of >±20um/1dB
(red curve) compared to direct fiber coupling tolerance (blue curve).

PhotonicBump technology

PhotonicBump aligns photonics with standard semiconductor manufacturing, packaging and testing flow. PhotonicBump is an add-on element implemented on silicon photonics wafers. It allows:

  • Beam deflection optics for wide-band surface coupling to replace the complicated side-coupling geometry.
  • Mode-conversion for matching waveguide and single-mode fiber spot sizes.
  • Large assembly tolerances: through the “self-aligning” optical arrangement.
  • Wafer level testing: allows surface probing of silicon photonic wafer prior dicing.
  • Planer separation between fibers and silicon photonic chip for efficient optical and electrical packaging.
PhotonicBump for WDM chip: wafer level optics for beam deflection, mode conversion and “self-aligning optics”.
PhotonicBump for grating coupling based chip for beam expansion and "self-aligning optics".
PhotonicBump planer separation for optical and electrical packaging. All optical and electrical I/Os are connected by means of single flip-chip assembly

Wide-Band Surface Coupling

PhotonicBump incorporates beam deflection optics optimized for WDM silicon photonic chip. It enables wide-band surface coupling thus avoids the complexity of typical fiber’s side coupling.

Wide-band surface coupling provides optical access for silicon photonics wafer level inspection.

PhotonicBump’s wafer level optics for wide-band surface coupling and wafer level inspection

Detachable fiber connectivity

Detachable fiber connectivity: detachable and serviceable fiber connectivity for post-reflow assembly optimized for co-packaged optics.

Large number of fibers: wafer level optics compatible with fiber high count.

Seamless optical/electrical integration: Flexible optical and electrical bumps for scalable optical and electrical packaging.

PhotonicPlug high channel count scalability.
Detachable PhotonicPlug optimized for multifiber applications and post reflow assembly.
PhotonicPlug 32 fibers packaged on silicon photonics chip through electrical interposer. Demonstrates a seamless optical/electrical packaging.
Photonics can now be seamlessly integrated with electronics and our customers can benefit from high bandwidth and low power consumption